A reconfigurable logic circuit as typified by a field programmable gate array (FPGA) realizes a predetermined logic (circuit configuration) based on data stored in a configuration memory.
As main circuit components of a FPGA, there are a LUT (look-up-table) realizing an arbitrary truth table and a MUX (multiplexer) selectively outputting a predetermined signal from among a plurality of input signals.
The conventional LUT is structured with configuration memories and a selection circuit unit. The LUT outputs data stored in one of the configuration memories selected by the selection circuit according to an input signal.
The conventional MUX is structured with a configuration memory and a selection circuit. The MUX outputs one input signal selected by the selection circuit from among a plurality of input signals according to data stored in the configuration memory.
In this way, because the conventional LUT and MUX are respectively structured by one or more configuration memories and a selection circuit, they have comparatively large circuit sizes. Therefore, the conventional LUT and MUX have had such a problem in that a chip area being large, or a signal delay being long.